Abstract: This paper describes the redesign and extension of an old but effective educational CPU visual simulator. The main goal is to support novices in understanding the behaviour of the key components of a CPU, focusing on how code written in high-level languages is actually executed on the hardware of a computer. Extensions include the addition of CPU flags and related conditional jump instructions to better illustrate the control flow in low-level languages; the possibility to define and use labels for numerical addresses, in order to clarify the concept of variable as well as the mapping of high-level programming constructs to assembly language; enhanced color-coded animations to better understand the sequential nature of the control unit and the role of the control bus in addition to the address and data buses. While the old simulator was based on a Harvard architecture, the new one is based on the classical Von Neumann architecture, to illustrate in simpler terms the concept of stored-program computer. Additional enhancements include a new, more realistic, compare instruction (with two addressing modalities), bit-wise logical operations, and operational improvements such as simulation speed control and better code editing functionalities. The new simulator has been developed following an Open Pedagogy / OER-enabled pedagogy approach, where a group of students incrementally modified the old simulator as part of their educational activities. This approach reduced the time spent on “disposable” traditional assignments, challenging students to address a real-world professional problem. Making available the result of these efforts with an open licence, we aspire to contribute to a self-fuelling cycle which will hopefully continuously improve and extend the resource for future students and teachers.
PPIG 2021 - 32nd Annual Workshop
An educational CPU Visual Simulator